1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a multilevel mask ROM (Read Only Memory) of an ion implantation type in which each memory cell stores multilevel data.
2. Description of the Prior Art
A mask ROM is also called a fixed ROM, and by using a mask including user data upon a wafer fabrication process, the mask ROM is manufactured having the data stored therein. In the mask ROM, individual data are stored in memory cells each composed of a piece of cell transistor. Formerly, the memory cell was arranged to store binary data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d according to a state of whether a bit line was connected or not connected to the cell transistor. However, recently, the technique in which the threshold voltage Vth of each the cell transistor generally made of a MOS (Metal-Oxide-Semiconductor) FET (Field Effect Transistor) is adjusted by using such as an ion implantation technique to make each cell transistor store adjusted binary data, thereby increasing a storage capacity of a mask ROM. In case of the mask ROM which stores data by changing the threshold voltage Vth in this way, a reference cell of the same structure as the memory cell which stores data is provided in the ROM in advance, and a reference current to be obtained from the reference cell and a current which flows in the memory cell at a read time are compared to reproduce the binary data.
Moreover, for the purpose of further increasing the storage capacity, a technique has been developed lately in which a plurality of bit data can be stored in each memory cell by making each memory cell store one of the multilevel data of three or more levels. A mask ROM in which each memory cell is arranged to store multilevel data of three or more levels in this way is called a multilevel mask ROM.
In the multilevel mask ROM, the threshold voltage Vth of the cell transistor of each memory cell is changed by ion implantation according to multilevel data to be stored in the memory cell. If the write data to be input to each memory cell is the data of N-level, a threshold voltage corresponding to the write data is selected from among threshold voltages of N kinds and set in the cell transistor of the memory cell. In this multilevel mask ROM, Nxe2x88x921 pieces of reference cells having different threshold voltages are provided beforehand. The structure of the reference cell is identical to that of the memory cell, and a current which flows in the memory cell at the read time and a reference current to be obtained from each reference cell are compared to reproduce the multilevel data. The reference current is compared as a criterion for distinguishing data with a current which flows when the cell transistor of the memory cell is switched on with its threshold voltage.
For example, if it is assumed that N=4, threshold voltages for the cell transistor of the memory cell are Vt0 to Vt3, and Vt0 less than Vt1 less than Vt2 less than Vt3, then the threshold voltages of the cell transistors of the reference cells are set to the same threshold voltages Vt0 to V12, respectively, as those of the cell transistors of the memory cells. The reference current is set by providing a predetermined offset by means of such as a known offset circuit so that th e reference current becomes approximately an intermediate value of each current which flows whe n the memory cell is switched on with each threshold voltage.
Since the predetermined data is stored by changing the threshold voltage of the cell transistor made of a MOSFET through an ion implantation process , the ion implantation process is also called code ion implantation process.
FIG. 1 is a block diagram showing the general structure of a multilevel mask ROM. Here, the multilevel mask ROM is a 4-level mask ROM in which each memory cell stores one of 4-level data.
The multilevel mask ROM comprises memory cell 21 for storing data, sense amplifier 22 for reading data from memory cell 21, a first, second and third reference cells 23a to 23c to be used as criteria against memory cell 21, a first, second and third reference amplifiers 24a to 24c for producing reference currents by using reference cells 23a to 23c, respectively, comparison circuit 25 for discriminating data stored in memory cell 21 by comparing the output of sense amplifier 22 and the output of each of reference amplifiers 24a to 24c, and logic synthesis circuit 26 for outputting 2-bit data through logic synthesis of the output result of comparison circuit 25. Here, the reference current is the current which serves as the criterion for distinguishing data stored in memory cell 21. In FIG. 1, although there is illustrated only one memory cell 21, a plurality of memory cells are actually disposed as a memory cell array, and by receiving an address from the outside, a memory cell corresponding to the address is selected. As a result, sense amplifier 22 reads the data from the selected memory cell to output it to comparison circuit 25.
Memory cell 21 and reference cells 23a to 23c each has a cell transistor made of a MOSFET, having the same structure. The threshold voltage of the cell transistor can be set to a desired value by changing the amount of ion to be injected to a channel region provided directly under the gate o f the cell transistor. Now, since the 4-level mask ROM is taken into consideration, memory cell 21 is set to any one of threshold voltages of Vt0, Vt1, Vt2 and Vt3 (where Vt0 less than Vt1 less than Vt2 less than Vt3) corresponding to its data stored. In order to distinguish these data of 4-level, the threshold voltages of cell transistors of a first, second and third reference cells 23a to 23c are set to Vt0, Vt1 and Vt2, respectively.
Further, with reference to a first, second and third reference amplifiers 24a to 24c, prescribed offsets are provided respectively so that the respective reference currents become approximately the mean value of the currents which flow when the cell transistor of memory cell 21 is switched on with respective threshold voltages. Here, Vt0 is the threshold voltage of the cell transistor when no ions are injected to the channel region directly under the gate.
In the 4-level mask ROM of a like structure, for reproducing the data, the output of sense amplifier 22 and the output of the first reference amplifier 24a are first compared by comparison circuit 25. At this time, if the output of sense amplifier 22 is smaller than the output of the first reference amplifier 24a, it is determined that the threshold voltage of the corresponding memory cell 21 is Vt0. Then, comparison circuit 25 compares the output of sense amplifier 22 and the output of the second reference amplifier 24b, and when the output of sense amplifier 22 is between the output of the first reference amplifier 24a and the output of the second reference amplifier 24b, the threshold voltage of that memory cell 21 is determined as Vt1, Next, comparison circuit 25 compares the output of sense amplifier 22 and the output of the third reference amplifier 24c, and when the output of sense amplifier 22 is between the output of the second reference amplifier 24b and the output of the third reference amplifier 24c, the threshold voltage of that memory cell 21 is determined as Vt2. When the output of sense amplifier 22 is larger than the output of the third reference amplifier 24c, the threshold voltage of that memory cell 21 is determined as Vt3. By distinguishing the respective threshold voltages of memory cell 21 in this way, data stored in memory cell 21 can be reproduced. Here, description has been made with reference to the successive comparison made by comparison circuit 25 between the output of sense amplifier 22 and the output of each of reference amplifiers 24a to 24c, however, of course it is possible to prepare a circuit which allows parallel comparison.
By the way, in the semiconductor memory device such as a mask ROM, miniaturization of memory cells has progressed recently in proportion to the increase of the storage capacity thereof. With reference to the mask ROM of this sort, it is known that electric currents flow in the cell transistor are reduced by reason of being influenced by the write state of data written in memory cells disposed in the vicinity of the cell transistor. Therefore, the value of the reference current must be set to a value which can certainly distinguish the data even if the current which flows in memory cell 21 is minimum, that is, in the worst case condition (minimum).
As a technique for setting the value of the reference current in an optimum manner, Japanese Patent Laid-open No. 55094/1997 (JP, A, 09055094) has disclosed the technique, although it concerns binary (2-level) mask ROM. According to this technique, dummy cells are disposed around the reference cell provided in the 2-level mask ROM, each dummy cell having the cell transistor injected with ions in the channel region, thereby enabling the mask ROM to certainly correspond to the data even if the currents which flow in the memory cell is in the worst condition.
The structure of the reference cell and a method of manufacturing the reference cell will be described with reference to 4-level mask ROM as an example for the case when the reference cell of the multilevel mask ROM is manufactured by applying the technique disclosed in Japanese Patent Laid-open Gazette No. 55094/1997.
FIGS. 2 and 3 are views showing the structure of the region of such a 4-level mask ROM in which the reference cell is disposed, FIG. 2 being a plan showing the structure of the reference cell region, and FIG. 3 being a sectional side elevation viewed from the III-IIIxe2x80x2 line of FIG. 2. Further, FIGS. 4A to 4D are plans explaining, in order, the manufacturing process of the reference cell shown in FIGS. 2 and 3.
In FIGS. 2 and 3 the mask ROM comprises a plurality of parallelly disposed buried diffusion layers 13 made of n+-type silicon layer provided on p-type silicon substrate 19, and gate lines 14 made of polysilicon disposed orthogonally to buried diffusion layer 13. Further, buried diffusion layer 13 serves as a source region and a drain region of a cell transistor (MOSFET) and gate line 14 serves as a gate electrode of the cell transistor. Since buried diffusion layers 13 and gate lines 14 are disposed in a form of a lattice, the cell transistors are disposed in a matrix form. FIG. 2 illustrates nine pieces of cell transistors, and the cell transistor disposed at the center of them becomes reference cell 11. In channel region 15 provided directly under the gate of reference cell 11, ions are injected to set a desired threshold voltage to reference cell 11. In FIG. 2, each of eight cell transistors surrounding reference cell 11 is dummy cell 12. As a result, dummy cells 12 each formed to the same structure as reference cell 11 are disposed around reference cell 11. Further, between gate line 14 and channel region 15, and between gate line 14 and buried diffusion layer 13, oxide films 16 are provided for insulating them.
It is noted that cell transistors are disposed in a form of a matrix in this way commonly in a floor of the ask ROM including a region in which the reference cells are disposed and another region in which the memory cell array is disposed. However, dummy cells are disposed surrounding the reference cell in the reference cell region, while on the contrary in the memory cell array region, cell transistors construct memory cells respectively without having dummy cells.
Here, in this multilevel mask ROM, the highest threshold voltage is set to the cell transistor of dummy cell 12 among respective cell transistors in the region where the reference cell is provided. As shown in FIG. 3, when ions are injected into channel region 15 through the gate of the cell transistor, the ions diffuse into buried diffusion layer 13 which serves as a source region and a drain region of the cell transistor, thereby increasing the electric resistance of buried diffusion layer 13. Since the resistance of buried diffusion layer 13 increases as the ion injection quantity becomes larger, if ion injection amount of dummy cell 12 is set to a value which allows the threshold voltage to become the highest, a minimum current is caused to flow in reference cell 11. Consequently, the reference current then becomes equal to the minimum cell current of each memory cell of the memory cell array, and hence an operation margin of sense amplifier 22 or comparison circuit 25 are secured. In other words, a memory cell having the least cell current among memory cells of the memory cell array is reproduced by this reference cell 11. Generally, sense amplifier 22 or comparison circuit 25 is designed to make the reference current thereof coincide with the minimum value of the cell current of the memory cell. Therefore, when the reference current grows larger than the cell current of the memory cell, the operation margin of sense amplifier 22 becomes insufficient. If the power source is in the upper direction and the ground potential is in the lower direction of FIG. 2, a path of the current which flows in reference cell 11 becomes, for example, like current path 17 shown in FIG. 2.
For example, when the threshold voltage of the cell transistor of reference cell 11 is set to Vt1, in the conventional 4-level mask ROM, ions are injected into reference cell 11 to make the threshold voltage Vt1 and dummy cell 12 to make the highest threshold voltage Vt3.
A manufacturing process of the reference cell shown in FIGS. 2 and 3 will next be described with reference to FIGS. 4A to 4D. The following description will be made, for example, with reference to the case in which the threshold voltage of reference cell 11 is set to Vt1. The region of FIGS. 4A to 4D attached with cross hatching each shows that ion implantation is applied thereto in the corresponding stage.
As described above, in the 4-level mask ROM, reference cells having threshold voltages set to Vt0, Vt1 and Vt2, respectively, are provided. FIGS. 4A to 4D each shows only the reference cell in which the threshold voltage is set to Vt1, and reference cells having threshold voltages set to Vt0 and Vt2 are provided outside the regions shown in FIGS. 4A to 4D. When the threshold voltage is set to Vt2, ions are injected in a second ion implantation process later described to form the reference cell. When the threshold voltage is set to Vt0, ion implantation is not performed to the reference cell.
In this case, as shown in FIG. 4A, buried diffusion layer 13 and oxide film 16 are first formed on silicon substrate 19 to form the mask ROM substrate. At this stage, no ion implantation is applied to channel region 15. A resist film for ion implantation having an opening prepared corresponding to reference cell 11 is formed on the mask ROM substrate. Next, as shown in FIG. 4B, ions are injected into channel region 15 (see FIG. 3) by an amount required for setting the threshold voltage to Vt1 thereby forming reference cell 11.
Here, the ion implantation process for setting the threshold voltage to Vt1 is called a first ion implantation process. Successively, a second ion implantation process for setting the threshold voltage to Vt2 is performed in the same way as the first ion implantation process. Since the threshold voltage of reference cell 11 shown in FIGS. 4A to 4D is set to Vt1, the resist film formed on the region has no opening, and as shown in FIG. 4C, no ions are injected in this region through the second ion implantation process. Finally, on the mask ROM substrate for which the second ion implantation process is finished, a resist film to be used in ion implantation is formed being provided with an opening corresponding to dummy cell 12, and as shown in FIG. 4D, a required amount of ions for setting the threshold voltage to Vt3 is injected to channel region 15, thereby forming dummy cells 12. The ion implantation process for setting the threshold voltage to Vt3 is called a third ion implantation process. Thereafter, gate electrode 14 is formed to complete the mask ROM.
The first, second and third ion implantation processes described above are also the ion implantation processes for writing desired data into respective memory cells in the memory cell array shown FIG. 1. Memory cell 21, reference cells 23a to 23c and dummy cell 12 each having its own threshold voltage are formed in the same series of the ion implantation processes, that is, these three successive ion implantation processes.
However, in the conventional multilevel mask ROM as above, when the reference cell is formed and concurrently the memory cell is built in accordance with the process shown in FIGS. 4A to 4D, the current which flows in the memory cell sometimes becomes smaller than the estimated current due to dispersion in the manufacturing process, resultantly approaching the reference current. Therefore, the operation margin of the comparison circuit is reduced, and in the worst case, there occurs the possibility of misjudgment of the data.
An object of the present invention is to provide a semiconductor ROM device which can obtain a reference current for securely distinguishing data stored in the memory cell.
Another object of the present invention is to provide a method of manufacturing the semiconductor ROM device which can obtain the reference current for securely distinguishing data stored in the memory cell.
The object of the present invention can be achieved by means of the semiconductor read only memory (ROM) device comprising: a semiconductor substrate; a memory cell having a first cell transistor, the first cell transistor having a threshold voltage in accordance with an amount of ions injected to a channel region of the first cell transistor, the threshold voltage corresponding to multilevel data of three or more levels to be stored in said memory cell; a reference cell provided on the semiconductor substrate and having a second cell transistor while setting up an amount of ions to be injected to a channel region of the second cell transistor, the reference cell being used for generating a reference current which is compared with a current read out from the memory cell to discriminate the data stored in the memory cell; and a dummy cell provided on the semiconductor substrate and having a third cell transistor disposed adjacent to the second cell transistor, the third cell transistor having a channel region into which ions are injected simultaneously with the ions injected to the channel region of the second cell transistor.
Another object of the present invention can be achieved by the method of manufacturing a semiconductor read only memory (ROM) device which comprises a memory cell having a first cell transistor with a threshold voltage in accordance with an amount of ions injected to a channel region of the first cell transistor, the threshold voltage corresponding to multilevel data of three or more levels to be stored in the memory cell; a reference cell having a second cell transistor for generating a reference current which is compared with a current read out from the memory cell to discriminate the data stored in the memory cell; and a dummy cell having a third cell transistor disposed adjacent to the second cell transistor, the method comprising the steps of: forming a resist film which is opened corresponding to the reference cell and the dummy cell disposed around the reference cell; and injecting ions simultaneously to the channel regions of the reference cell and the dummy cells by using the resist film as a mask.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.